1. Field of the Invention
The present invention relates to a photomask, a semiconductor device, and a method for manufacturing a semiconductor device, and more particularly to a photomask that can prevent a resist film from deteriorating during manufacturing, a semiconductor device manufactured by using the photomask, and a method for manufacturing a semiconductor device by using the photomask.
2. Description of Related Art
Improved integration has been constantly demanded of semiconductor devices such as a dynamic random access memory (DRAM). To achieve this, the processing dimensions of photolithography have been made smaller. Among the miniaturization techniques is oblique incidence illumination.
If a photomask having a line-and-space pattern (hereinafter, referred to as a “LS pattern”) is irradiated with vertical light, ±1st-order diffraction beams occur in addition to a 0th-order beam. The two types of ±1st-order diffraction beams are also converged on a wafer through a lens. As the pattern becomes finer, it has become difficult to converge the 0th- and ±1st-order, three types of beams on a single point on the wafer. The oblique incidence illumination is a method for irradiating a photomask with light in an oblique direction so that 0th- and +1st-order, or 0th- and −1st-order, two types of beams are converged for an improved processing accuracy. The oblique incidence illumination can reduce the resolution limit dimensions to approximately ½ as compared to typical illumination in a vertical direction.
Dipole illumination, a type of oblique incidence illumination, improves resolution by irradiating a photomask with light in two directions oblique to an optical axis. For example, a dipole illumination method using two light sources (two poles) arranged on an X-axis improves resolution in the X-axis direction. Such a method is effective for an LS pattern in which opening traces are repetitively arranged in the X-direction. For an LS pattern in which opening traces are repetitively arranged in both X- and Y-axis directions, a cross-pole illumination method using two poles arranged on the X-axis and two poles on the Y-axis, i.e., a total of four poles may be used.
As the degree of integration of semiconductor devices increases, wiring is also becoming finer. Since aluminum wiring is difficult to ensure sufficient reliability, damascened copper wiring is now in the mainstream. Damascened copper wiring is generally formed by the following process.
Initially, an interlayer insulation film such as a silicon oxide film is formed on a semiconductor substrate. A resist film is formed on the interlayer insulation film. Next, an opening pattern of wiring grooves is formed in the resist film by photolithography. Using the resist film having the opening pattern as a mask, the interlayer insulation film is etched to form wiring grooves. Wiring materials such as titanium nitride and copper are embedded into the wiring grooves. The wiring materials lying over the interlayer insulation film are removed by chemical mechanical polishing (CMP) to form copper wring along the wiring grooves (see Japanese Patent Application Laid-Open No. 2009-123878).
As described above, the damascening does not pattern the wiring materials themselves but etches the interlayer insulation film to form wiring grooves. Copper is difficult to pattern by dry etching. When using copper as a wiring material, the damascening is often employed to etch the interlayer insulation film which is easier to process than copper. The foregoing oblique incidence illumination is used when forming the wiring grooves as a LS pattern.
Minimum wiring dimensions have recently been approaching the resolution limit of the photolithographic techniques. The present inventor has recognized the possibility that a resist film can be partly thinned when a fine LS pattern of wiring close to such a resolution limit is formed. More specifically, the present inventor has found that if a photomask has a plurality of opening traces arranged close to each other, the resist film near the ends of an opening trace can be excessively reduced to possibly cause a short circuit of wiring.